Circuit for suppressing voltage jitter and method thereof

ABSTRACT

A voltage jitter suppression circuit and a method thereof are disclosed. The circuit is utilized for alleviating the voltage jitter phenomenon of an IC. Regardless of the circuit frequency and voltage, the voltage jitter phenomenon of the circuit can be improved significantly by utilizing the present invention.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an electronic circuit, and moreparticularly, to an electronic circuit for suppressing a jitter noise involtage Vdd in an integrated circuit (IC).

2. Description of the Prior Art

Integrated circuit (IC) designers nowadays pay much more attention tohigh speed and low voltage design issues. The parasitic inductancegenerated due to the packaging of an IC such as wire bonding has asignificant influence on the internal circuitry of the IC. For example,a voltage jitter phenomenon is generated by the power. The voltagejitter phenomenon will reduce the circuit performance significantly,especially in IC designs related to high frequency and low voltage.

The conventional methods for suppressing the voltage jitter phenomenoninclude utilizing a better packaging scheme and utilizing a multiplebonding wire scheme (such as three-fold, four-fold, or five-fold bondingwire schemes). FIG. 1 shows a simplified block diagram 100 of thefive-fold bonding wire scheme according to conventional art. In thisconventional art, a chip 102 includes a pin 104, a plurality of powerbonding pads 105-109, a plurality of bonding wires 110-114, and anequivalent capacitor 120, wherein the plurality of bonding wires 110-114have an inductance value, and the plurality of bonding wires 110-114 arecoupled to the pin 104 and the power bonding pad 105-109 respectively.The power bonding pads 105-109 are coupled to a power terminal insidethe chip 102. Theoretically, the greater the number of bonding wires,the better the suppressing effects. The conventional methods apply thetheory of more inductances connected in parallel generating a smallerequivalent inductance value, so as to reduce the effective parasiticinductance value. The purposes of these two conventional arts are bothto reduce the parasitic inductance value and to suppress negativeperformance impacts resulting from voltage jitter.

Conventional methods utilizing a better packaging scheme or more bondingwires require more bonding pads, and thus a larger chip area toaccommodate the increased number of bonding pads. Thus, conventionalmethods suffer from higher packaging and wire bonding costs. Thecompetitiveness of the IC is based on the circuit performance and itsmanufacturing cost. Thus, improving IC performance while lowering costis a perpetually important issue for IC design researchers.

SUMMARY OF THE INVENTION

It is therefore one of the objectives of the present invention toprovide a circuit for suppressing voltage jitter in order to solve theabove-mentioned problems. Such a circuit for suppressing voltage jitterwill provide a solution for the current and future trends of low voltageand high frequency circuits. To lower costs, the voltage jittersuppression circuit need not use too many bonding pads or a betterpackaging scheme.

A voltage jitter suppression circuit of the present invention includes apin; a first bonding pad; a first bonding wire, coupled between the pinand the first bonding pad, having a first inductance; and a dampingimpedance coupled between the power line and the first bonding pad.

A method for alleviating a voltage jitter of a power line of anintegrated circuit (IC) of the present invention includes providing apin and a first bonding pad; providing a first bonding wire coupledbetween the pin and the first bonding pad, wherein the first bondingwire has a first inductance; and providing a damping impedance coupledbetween the power line of the IC and the first bonding pad.

Next, an impedance value of the damping impedance can be adjustedaccording to the differences between the values of the elements insidethe equivalent circuit composed of the elements mentioned above, inorder to attain the requirement of alleviating the voltage jitterbetween the two terminals of the equivalent circuit as quickly aspossible.

The damping impedance value of the equivalent circuit architecture isnot only able to restrain the voltage jitter phenomenon efficiently soas to improve the performance of the circuit, but can also indirectlyreduce the chip cost since the number of I/O pins outside the chip issubstantially decreased.

Regardless of the circuit frequency and voltage, the voltage jitterphenomenon of the circuit can be improved significantly by utilizing thepresent invention according to the above description. In addition, thechip cost will also be reduced since it is not required to increase thenumber of the bonding pads.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a simplified block diagram of a five-fold bonding wirescheme according to conventional method.

FIG. 2 shows a simplified block diagram of a voltage jitter suppressioncircuit according to an embodiment of the present invention.

FIG. 3 is an equivalent circuit diagram of FIG. 2.

FIG. 4 shows a V(t) simulation result of the equivalent circuit diagramof FIG. 2.

FIG. 5 shows a simplified block diagram of a voltage jitter suppressioncircuit according to another embodiment of the present invention.

FIG. 6 shows a result obtained by a computer simulation according to anembodiment of the present invention and a conventional five-fold bondingwire scheme.

DETAILED DESCRIPTION

FIG. 2 shows a simplified block diagram of a voltage jitter suppressioncircuit according to an embodiment of the present invention. As shown inFIG. 2, the voltage jitter suppression circuit 200 includes a pin 204, afirst bonding pad 206, a second bonding pad 208, a first bonding wire210, a second bonding wire 212, a damping impedance 214, and a capacitor216. The first bonding wire 210 and the second bonding wire 212 have afirst inductance value and a second inductance value, respectively, andare equivalent to a parasitic inductance of the pin 204 and the firstbonding pad 206 and a parasitic inductance of the pin 204 and the secondbonding pad 208, respectively. The first bonding wire 210 is coupledbetween the pin 204 and the first bonding pad 206, and the secondbonding wire 212 is coupled between the pin 204 and the second bondingpad 208. The first bonding pad 206 is coupled to a power line inside thechip 202, wherein the power line can be a high voltage level power line(such as Vdd) or a low voltage level power line (such as Vss, GND)inside the chip 202. The damping impedance 214 is coupled between thepower line inside the IC and the second bonding pad 208, and thecapacitor 216 is utilized to be equivalent to a capacitance between thehigh voltage level power line and the low voltage level power line. Inanother embodiment, the first bonding pad 206 and the first bonding wire210 can be omitted.

In another embodiment, an impedance value of the damping impedance 214is adjustable. The impedance value of the damping impedance 214 beadjusted to attain the requirement of alleviating the voltage jitterbetween the two terminals of the equivalent circuit.

FIG. 3 shows an equivalent circuit diagram 300 of FIG. 2. in theequivalent circuit diagram 300, a second inductance 304 represents thesecond bonding wire 212, a impedance 306 represents the dampingimpedance 214, and a first inductance 302 representing the first bondingwire 210, and a capacitor 310 represents the capacitor 216. In thisequivalent circuit 300, a signal source provide a unit step functionsignal which is presumed to be input to simulate ea practical circuit.Here, the present invention utilizes a Laplace transformation tocalculate V(s)=I(s)Z(s), and two characteristic formulas of theequivalent circuit diagram 300 can be obtained as follows:

${Z(s)} = \frac{{s\; L_{2}L_{1}} + {s\; L_{1}R_{s}}}{{s^{3}L_{2}L_{1}C_{1}} + {s^{2}L_{1}C_{1}R_{s}} + {s\left( {L_{2} + L_{1}} \right)} + R_{s}}$${V(s)} = {\frac{Z(s)}{s} = \frac{{L_{2}L_{1}} + {L_{1}R_{s}}}{{s^{3}L_{2}L_{1}C_{1}} + {s^{2}L_{1}C_{1}R_{s}} + {s\left( {L_{2} + L_{1}} \right)} + R_{s}}}$

A V(t) simulation result of the equivalent circuit diagram 300 of FIG. 2can be obtained according to the above characteristic formulas, and thesimulation result is shown in FIG. 4. It is known that when an impedancevalue of the damping impedance 306 is too large (such as 1000 ohms) ortoo small (such as 1 ohm), the V(t) has a more serious noise jitter. Aslong as the impedance value of the damping impedance 306 is close to aspecific value (such as 46 ohms), the jitter will be smaller anddisappear faster. Of course, the impedance value of the dampingimpedance 306 can be adjusted to reduce and stabilize the jitter of theV(t) more quickly. In other words, the impedance value of the dampingimpedance 306 is determined according to the values of the internalelements of the equivalent circuit diagram 300.

In an embodiment, the damping impedance 306 is a resistance element, andin a preferred embodiment, the damping impedance 306 is an adjustableresistance circuit. The adjustable resistance circuit receives a controlsignal (which is transmitted from a control circuit of FIG. 5, forexample), and the adjustable resistance circuit provides a correspondingresistance value according to the control signal. In a preferredembodiment, the control signal is transmitted from at least a controlregister, and the value of the control signal stored in the controlregister can be set directly or indirectly by a software or a firmwareor after automatic detection. In another embodiment, the adjustableresistance circuit is a resistance network circuit including a pluralityof resistance elements and at least one corresponding switch, whereinthe resistance value is adjusted by controlling whether thecorresponding switch is ON or OFF to change the connection scheme (whichcan be a series connection scheme or a parallel connection scheme) ofthe plurality of resistance elements. For example, the number of theseries connection or the parallel connection can be changed. Inaddition, the switch is controlled by the control signals.

The inductance values of the first bonding wire 210 and the secondbonding wire 212 in FIG. 2 can only be estimated in advance, and theseactual inductance values of the first bonding wire 210 and the secondbonding wire 212 cannot be controlled precisely. Please refer to FIG. 5.FIG. 5 shows a simplified block diagram of a voltage jitter suppressioncircuit according to another embodiment of the present invention. Incomparison with FIG. 2, there is an additional control circuit 517 inFIG. 5. The control circuit 517 is utilized for receiving the voltagesignal, and for monitoring or detecting a voltage variation of thevoltage signal, so the control circuit 517 can output a proper controlsignal according to the voltage variation of the voltage signal toadjust the resistance value of the adjustable resistance circuit 514 soas to attain better efficiency in suppressing the voltage jitter.

The control circuit 517 has many embodiments. For example, the controlcircuit 517 includes a detecting unit 518 and a control logic unit 519,wherein the detecting unit 518 is a counter. The control logic unit 519sets an impedance value of the damping impedance 514 in advance, andthen generates voltage jitter; for example, utilizes at least a controlswitch element and a current source to transiently change a current toinduce the voltage jitter. In the meantime, the counter is utilized forcounting a jitter number of the voltage signal in a predetermined timeto generate a counting value and providing the counting value to thecontrol logic unit 519. A plurality of counting values corresponding tothe different impedance values of the damping impedance 514 can beobtained by utilizing the control logic unit 519 to perform the abovesteps repeatedly, so a better impedance value of the damping impedance514 can be determined from the plurality of counting values (i.e. asmallest counting value is determined from the plurality of countingvalues, and a corresponding impedance value is found according to thesmallest counting value), and a proper control signal is output. Inanother embodiment, the detecting unit 518 can be an analog-to-digitalconverter (ADC). In this embodiment, the ADC outputs digital signalsrepresenting the voltage variation of the voltage signal. The controllogic unit 519 receives and records the digital signals representing thevoltage variation of the voltage signal, and determines a digital signalrepresenting the smallest voltage variation (for example, byaccumulating a value difference of two adjacent digital signals, and ifthe accumulation value is the smallest, this means that the jitter isthe smallest) so as to determine a better impedance value. In anotherembodiment, the detecting unit 518 can be a comparator for receiving thevoltage signal and a reference voltage. When the voltage variation ofthe voltage signal is larger, the number of output value variationoccurrences (i.e. the number of transitions between the “high level” andthe “low level”) from the comparator will be higher. When the voltagevariation of the voltage signal is smaller, the number of comparatoroutput variations will be fewer, and thus the control logic unit 519 candetermine a better impedance value according to the number of times ofthe transition. The control circuit 517 can operate in a normaloperation mode (with fixed intervals or arbitrary intervals), acalibration mode, or a power-up mode (during an initial stage of turningon the circuit). In an embodiment, the control signal generated by thecontrol circuit 517 is stored in a storing unit (not shown) in thecalibration mode; the storing unit is utilized for outputting thecontrol signal and the control circuit 517 is disabled in the normaloperation mode. The storing unit can be any element with a storingfunction such as a register, all kinds of memories, a buffer, etc.

FIG. 6 shows two results obtained by a computer simulation according toan embodiment of the present invention and a conventional five-foldbonding wire scheme. As shown in FIG. 6, it is obvious that theembodiment of the present invention has a significant effect incomparison with conventional multiple bonding wire methods.

The present invention is not only able to restrain the voltage jitterphenomenon efficiently and improve circuit performance, but alsoindirectly to reduce the chip cost since the number of I/O pins outsidethe chip is effectively decreased. Since the voltage jitter phenomenonis efficiently suppressed, for the internal circuit of the chip, theprobability of an operation error due to noise interference will bereduced. The present invention is especially suitable for application ina circuit with a low voltage source, or a digital circuit, or a digitalcircuit of a low voltage source, because circuits with low voltagesources and digital circuits tend to be particularly susceptible tovoltage jitter.

Regardless of the circuit frequency and voltage, the voltage jitterphenomenon of the circuit can be improved significantly by utilizing thepresent invention.

Those skilled in the art will readily observe that numerousmodifications and alterations of the device and method may be made whileretaining the teachings of the invention.

1. An apparatus of an integrated circuit (IC) for alleviating a voltagejitter of a power line of the IC, comprising: a pin; a first bondingpad; a first bonding wire, coupled between the pin and the first bondingpad, having a first inductance; and a damping impedance coupled betweenthe power line and the first bonding pad.
 2. The apparatus of claim 1,wherein an impedance value of the damping impedance is adjustedaccording to a control signal.
 3. The apparatus of claim 2, furthercomprising: a storing unit, for storing the control signal.
 4. Theapparatus of claim 1, further comprising: a control circuit, coupled tothe damping impedance, for monitoring a voltage variation of the powerline to output a control signal, wherein an impedance value of thedamping impedance corresponds to the control signal.
 5. The apparatus ofclaim 4, wherein the control circuit is disabled after the controlsignal is stored in a storage unit.
 6. The apparatus of claim 4, thecontrol circuit comprising: a detecting circuit, for monitoring thevoltage variation of the power line to output a detecting result; and acontrol logic unit, coupled to the detecting circuit, for outputting thecontrol signal according to the detecting result.
 7. The apparatus ofclaim 6, wherein the detecting circuit further comprises a counter forcounting the voltage jitter of the power line to output the detectingresult.
 8. The apparatus of claim 6, wherein the detecting circuitfurther comprises a comparator for comparing a voltage signal of thepower line with a reference voltage to output the detecting result. 9.The apparatus of claim 4, wherein the IC further comprises an internalcircuit, and the control circuit is enabled during an initial stage ofthe internal circuit.
 10. The apparatus of claim 1, wherein theapparatus changes the impedance value of the damping impedancesuccessively so as to generate a plurality of detecting results, anddetermines the impedance value of the damping impedance according to theplurality of detecting results.
 11. The apparatus of claim 10, whereinthe apparatus actively induces the voltage jitter of the power line in acalibration mode.
 12. The apparatus of claim 11, wherein the apparatusinduces the voltage jitter of the power line by a transiently changingcurrent.
 13. The apparatus of claim 1, wherein the damping impedancefurther comprises a plurality of resistance elements and a plurality ofswitch elements, and a control signal is utilized to control theplurality of switch elements so as to adjust an impedance value of thedamping impedance.
 14. The apparatus of claim 1, further comprising: asecond bonding pad coupled to the power line; and a second bonding wirecoupled between the pin and the second bonding pad.
 15. The apparatus ofclaim 1, wherein an impedance of the damping impedance is correspondingto the first inductance.
 16. A method for alleviating a voltage jitterof a power line of an integrated circuit (IC), comprising: providing apin and a first bonding pad; providing a first bonding wire coupledbetween the pin and the first bonding pad, wherein the first bondingwire has a first inductance; and providing a damping impedance coupledbetween the power line of the IC and the first bonding pad.
 17. Themethod of claim 16, wherein an impedance value of the damping impedanceis adjusted according to a control signal.
 18. The method of claim 16,further comprising: monitoring the voltage of the power line to output acontrol signal, wherein an impedance value of the damping impedancecorresponds to the control signal.
 19. The method of claim 18, the stepof monitoring further comprising: counting the voltage jitter of thepower line at different times to generate a plurality of countingresults; and outputting the control signal according to the plurality ofcounting results.
 20. The method of claim 18, the step of monitoringfurther comprising: comparing the voltage of the power line with areference voltage at different times to output a plurality of comparingresults; and outputting the control signal according to the plurality ofcomparing results.
 21. The method of claim 18, wherein before themonitoring step, the method further comprises: inducing the voltagejitter of the power line in a calibration mode.
 22. The method of claim18, wherein the step of monitoring is disabled after the control signalis stored.
 23. The method of claim 16, further comprising: providing asecond bonding pad; and providing a second bonding wire coupled betweenthe pin and the second bonding pad.
 24. The method of claim 16, whereinan impedance of the damping impedance is corresponding to the firstinductance.